ttb_gen_plus_2B has been updated with a bug fix.
The Beta version of ttb_gen_plus had a re-write when I first released it, a couple months back. The parsing was updated to include multi-pin definitions on the same line, like the real syntax allows. I personally do not use that syntax, I only define one pin per line in an entity definition. So there was quite a bit of code change, and I did not test one case. The bug was that if you have an inline comment in the entity definition such as PIN_NAME : std_logic; -- inline comment, the comment would be considered pins and create incorrect output.
The bug was fixed by stripping off trailing comments from the code lines as they are read from the file. One little case I just did not consider nor test for. The new version of ttb_gen_plus_2B is v2.02. It can be downloaded from here ttb_gen_plus_B2.
If you are using the Beta version of the VHDL test bench package, and old version of ttb_gen_plus was included with that package. To take advantage of the bug fix you will have to download the newest version as linked above.
If you have any problems with or suggestions for the ttb_gen_plus tool, please add a comment to this post or email me.
Sckoarn
The Beta version of ttb_gen_plus had a re-write when I first released it, a couple months back. The parsing was updated to include multi-pin definitions on the same line, like the real syntax allows. I personally do not use that syntax, I only define one pin per line in an entity definition. So there was quite a bit of code change, and I did not test one case. The bug was that if you have an inline comment in the entity definition such as PIN_NAME : std_logic; -- inline comment, the comment would be considered pins and create incorrect output.
The bug was fixed by stripping off trailing comments from the code lines as they are read from the file. One little case I just did not consider nor test for. The new version of ttb_gen_plus_2B is v2.02. It can be downloaded from here ttb_gen_plus_B2.
If you are using the Beta version of the VHDL test bench package, and old version of ttb_gen_plus was included with that package. To take advantage of the bug fix you will have to download the newest version as linked above.
If you have any problems with or suggestions for the ttb_gen_plus tool, please add a comment to this post or email me.
Sckoarn
Hi
ReplyDeleteI think there is a bug in the latest ttb_gen_plus_2B bug fix version.
It appears that it does not like component declared within architecture. See the example below:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity trimode_top is
generic (
REC_RE_MODE_CH1 : std_logic := '0' -- 1=REC Mode, 0=RE Mode
);
port (
FPGA_DEBUG15 : out std_logic
);
end;
architecture struct of trimode_top is
component uart_top
port (
op_txrdy : out std_logic -- goes to status register for polling
);
end component;
end;
The utility prodeces:
dut: trimode_top
-- generic map(
-- )
port map(
fpga_debug15 => temp_fpga_debug15,
architecture => temp_architecture,
struct => temp_struct,
of => temp_of,
trimode_top => temp_trimode_top,
iscomponent => temp_iscomponent,
uart_topport => temp_uart_topport,
(op_txrdy => temp_(op_txrdy
);
David
Thanks David,
DeleteI will look into this and try and replicate the problem. It is hard to code a language parser in tcl. I have tried to compensate for all syntax and though I had it ...
I hope you were able to work around this problem.
If you get a moment please zip up the full code file you are
running the ttb_gen_gui on. That would help me debug the problem. Send zip file to sckoarn.vhdl@gmail.com
Sckoarn