VHDL Test Bench Package: ttb_gen_plus_2B Bug Fix

ttb_gen_plus_2B has been updated with a bug fix.
The Beta version of ttb_gen_plus had a re-write when I first released it, a couple months back. The parsing was updated to include multi-pin definitions on the same line, like the real syntax allows. I personally do not use that syntax, I only define one pin per line in an entity definition. So there was quite a bit of code change, and I did not test one case. The bug was that if you have an inline comment in the entity definition such as PIN_NAME : std_logic; -- inline comment, the comment would be considered pins and create incorrect output.

The bug was fixed by stripping off trailing comments from the code lines as they are read from the file. One little case I just did not consider nor test for. The new version of ttb_gen_plus_2B is v2.02. It can be downloaded from here ttb_gen_plus_B2.

If you are using the Beta version of the VHDL test bench package, and old version of ttb_gen_plus was included with that package. To take advantage of the bug fix you will have to download the newest version as linked above.

If you have any problems with or suggestions for the ttb_gen_plus tool, please add a comment to this post or email me.

Sckoarn

VHDL Test Bench Package: A Partner Scripting Language

Using a partner language.

This blog entry will show how a “partner” language can be of great assistance to the verification effort. I am specifically referring to the many free scripting languages that are available, such as tcl/tk, perl, python, java ... I currently use tcl/tk as my partner language. I chose tcl because it is used by many tool vendors that provide simulators for HDL simulation. Many poohoo the choice of TCL, but what ever gets the job done is good. I found the GUI part of tcl/tk most interesting. The ability to whip together a small GUI that can do huge amounts of work, yet be intuitive to use, has increased my productivity. Specially because the GUI “script” is so easy and quick to put together.

This blog entry will also tie together topics mentioned in the Variables and Randomization posts.

In the following text, the word “script” refers to partner language code. The words “test case” and “stimulus file”, refer to test bench scripts that the VHDL Test Bench Package would parse.

One might ask, “What can a partner language do for me? After all, it is more code and yet another language to learn and more programs to maintain.”

To answer the first question, I have personally created scripts to do the following (to mention a few)

• Provide GUI interface representing DUT programmable features for test case writers
• Provide base stimulus file generation based on programmable features selected
• Provide auto generation of Register INCLUDE files for test cases
• Provide auto generation of Register indclude “.h” files for software
• RS-232 interface for dynamic configuration regressions on FPGA devices
• push button simulation regression
• simulation regression log viewing tool
• Random configuration and test case generation
• Register set and RAM test case generation
• Complicated Diff tool for specialized file diffing
• SUDOKO game
• TTBgen GUI
• assembler (for custom assembly code)

The GUI in the first point included the four proceeding points as part of it's functionality. This script grew to a size of 30000 lines in a matter of 5 years. In other words it evolved with the project from a simple test case generation tool to a hardware regression tool and even used in manufacturing. So the effort was seen as a good one, even though it took three to six months to become skillful in tcl/tk coding.

Test Case Generation:

The tool/script mentioned above was initially created to simplify the test case writing effort because the DUT was very complicated to program. There were many calculations to perform based on configuration settings. The output from the calculations produced values that had to be written to DUT registers and RAM. This effort proved to be too much for any team member to overcome and prompted the creation of the tool. The tool provided the user the ability to select and set functions and then view the resulting calculated values and register settings for the selected configuration. For each special functional block a “tab page” presented the registers and default values for user editing. Once the user was happy with all the values presented, a button could be hit to generate a stimulus file that could be used in simulations with the VHDL Test Bench Package. To re-assure the user that his configuration was what was wanted, a graphical representation of the configuration was also provided.

As we all know, register set definitions change as a design progresses. As suggested in the Variables blog post, a master file for holding register specifications are a good thing. As an aid to myself, I added some special function buttons on an Options “tab page” that enabled me to generate a variable DEFINE include file, for simulations. Also generated from the same master file were Register set test cases, RAM test cases and .h include files for software.

Of course during play time some of us program. I created a Sudoko program for fun. I learned how to use randomization, in tcl, through that effort. The Sudoko code, though ugly, does the job. I then proceeded to make it so the tool, at work, could randomize itself. The user could provide a “seed” and hit a button and a random configuration would be created. With a little more effort a RS-232 interface was created so that connection to the FPGA processor block could be done through a debug link. The randomly generated configurations were then be applied to the FPGA and each test was performed in real time. To help put this in perspective, 1024 random configurations could be tested on the FPGA in four hours. The same random configurations run in simulation, on one machine, would take 256 days. (assuming six hours per simulation) That is a huge time savings.

The above real life story demonstrates what can be achieved through the use of a scripting language. Not only were stimulus files generated but real time regressions were realized in the end. Each iteration of FPGA design had the 1024 random regression applied as a qualification for delivery to software.

When you are looking at the job of writing test cases, it may seem that the effort could never end. I have found the fastest way to reduce the effort is to create a test case generation program. The use of a GUI is recommended as it enables users to interact with a familiar medium. Presented by the GUI are all the functional buttons and knobs that can be set and adjusted in the DUT. Many, if not all, of the DUT functions can be represented by simple “check buttons” and fields for user interaction. To help get started, if you are interested in tcl/tk, feel free to use the TTBgen GUI tool as a template. Once familiar with language constructs, it is surprising how quickly an application can take shape.

Randomization:

Most modern scripting languages have a random function that can be used to produce randomization for your testing, through random test case generation. This can greatly reduce the time it takes to create test cases. As well, the quality of testing should be better when randomization is used.

For instance, if you are developing a CPU, a large set of random test cases would be nice to run in regressions. To create a large set of random test cases would take a person a long time to write. They would have to roll dice for each instruction to help them in getting some randomization included. If we consider a large set of test cases to be 200 each with 10,000 instructions, then there is many die rolls to be done. But if instead, the person took the time to learn and use a partner scripting language to generate those test cases for them, they gain twice. First the test cases can be generated much faster than can be written by hand and second, the person learned better how to use their partner language to assist them in their verification efforts. So now the question is not how to write all the test cases, but how to run them all in a decent time frame.

If your testing requirements lead you to have to create a complicated GUI, this in itself can be a blessing. The quickest way to get randomization is to provide a “Randomize” button and a “Seed” field. Make the tool randomize its own fields and then generate test cases from the random configuration. You will be surprised how quickly this can be done and how useful this will be.

If an FPGA is part of the design process, take advantage of it to assist in your over all testing. One thing to keep in mind is that, if you randomly generate configurations for FPGA regressions, be sure you can replicate those configurations in simulation. In a high paced development environment, you will most likely uncover some bugs while regressing on the FPGA. Being able to replicate the failing configurations in simulation will greatly enhance the debug effort.

I hope that it is now obvious how valuable a scripting language can be to your verification efforts.

I personally use TCL from ActiveState.

Sckoarn

The VHDL Test Bench Package: Randomization

Randomization ... a hot topic in the ASIC/FPGA verification world.

In VHDL, the IEEE math_real package, currently provides a method to generate random numbers through the uniform procedure. Getting a random number from uniform is a multi-step process and is not convenient to use. In the past I have used a LFSR construct coded in a procedure to generate random numbers. In stead of home cooking your own random number generation system or directly using uniform, I strongly recommend you look here:  SynthWorks Downloads   Specifically the random package RandomPkg_2_0. This free download, of source code and documentation, is a very capable package for generating random numbers. Besides the package content, the package also demonstrates some advanced VHDL 2008 coding techniques. The rest of this post will assume that the reader has reviewed or plans to review the SynthWorks' RandomPkg documentation and is familiar with the package and its definitions of randomization.

The VHDL Test Bench Package does not hinder the implementation of randomization. In fact, randomization may remove the need for scripts altogether. Taking randomization to the fullest, you may find that the tb_bhv file just becomes a container for your randomization objects and BFMs and no script is needed to make your simulations work. Randomization can be viewed from four different “levels”. With level one being simple randomization scripting instructions to enable a general randomization facility in scripts. Level two is the BFMs randomizing their output under the control of the scripting system, i.e. the stimulus bus. Level three is the randomization through randomly generated scripts. Finally at level 4, the system is completely controlled by an object that is able to generate random transaction based interaction with the BFMs. This post will cover the level 1 and 2 implementations and leave the level 3 and 4 for future posts.

The most obvious randomization within the scripting system would be to create a RAND_VAR instruction. Like the EQU_VAR (equate variable) instruction, provided by the test bench template, a RAND_VAR instruction could be created to randomize the contents of a variable. This variable could then be used as the address or data field in a write instruction, for instance. I am sure an implementer can come up with several other randomization type instructions for use in scripting. I have found that randomization be better done within a BFM.

There is an issue with random number generation that has to be addressed by the implementation. If for instance, we want to randomly write, random data, to a RAM as well as read back and verify that data, you will have to implement a more complex random number generation system. To re-state the problem, we want to randomize the address and data for both write and read operations. Lets also assume that we want to start reading and testing after four writes have been done. (This is done to offset the reads from writes, possibly uncovering some functional bug.) This can be done in one of two ways.

First, the write address and data could be stored in a FIFO construct, and reused for the read operations. This implementation causes the implementer to create two random numbers that have different random sequences. This is because the restrictions on address generation may not be the same as the data generation. If the address is sixteen bits wide and the data is only eight bits wide, the constraints on the two numbers being generated will be different. The address will be constrained to a number that fits in sixteen bits where the data generation will be constrained to fit within eight bits. The two numbers could be generated from a single random number stream, but that makes them dependent on each other. For instance, if I change the constraint on the address generation, that will effect the data values generated. The solution is to have more than one random number stream and in this case two. The reason for the two different random number streams, is because you may want to randomize both independent of each other. So, for one randomly generated address stream, you can generate many different random data streams.

Second, four different random number streams could be implemented and used to create a test to randomly test the RAM. The write and read data random variables could be initialize with the same seed and a different seed used for the write and read data.

Confused yet? A review of the SynthWorks' Random_Pkg documentation may help. I will attempt to make it clear here as well. For each random number stream that you want to have concurrently generating random numbers, you need to have a variable of type RandomPType defined. The RAND_VAR instruction will have to be expanded to include an index to random number stream to be used for the random operation. The RAND_VAR instruction should also have, as parameters, the max and min values to constrain generation within. This makes the simple RAND_VAR instruction much more complicated to implement in a script as it requires the script writer to understand and manage random number generation streams. If possible, the implementer should try to avoid complication in the scripts and move it into a BFM.

In a level 2 implementation, as defined above, the randomization is done within a BFM. This can hide complication from the script system. For items to be generated randomly a variable for each can be defined giving complete sequence independence for all fields.

Lets take an ATM signalling BFM as an example. The packet fields include GFC, VPI, VCI, PTI, CLP, HEC and data. One of the modes of operation for this BFM is random generation for any combination of fields. Through the stimulus access port, registers can be written to set the BFM to operate in different modes as well as provide random generation limits. The test case writer now only has to set up the register set for the configuration and not worry about the random number sequences. The sequences of random numbers will be controlled by the implementation of the BFM randomization system.

A simple example of random generation in a BFM is presented in the packet_gen example. This is part of the current Beta VHDL Test Bench Package download:  Beta Test Bench Package

In the coming weeks, I will be posting a full set of BFM's for an environment to test a simple self threading switch. This will enable example code of a complete randomization system to be presented, with enough complexity to take the example into a master BFM implementation. I am currently working on coding this example DUT and test bench. Until the example is released, there is enough information in this post to keep some busy playing with randomization.

Sckoarn

VHDL Test Bench Packge: Version 2 Beta Release

 The version 2 VHDL Test Bench Package Beta is now available.

This version of the package introduces very few changes. The main addition to the package is the ability to have an undefined number of parameters for a command. The other addition is the predefined record types for the stimulus access bus. A minor change is the clean up of the package for commented out lines and unused functions. They were removed.

There is one bug fix in this issue. It seems the file_name variable had no return value from the access_inst_sequ procedure.

In order to create an instruction that has an undefined number of parameters, the “args” value, in the define_instruction call, must contain a value larger than six. This will cause the parser to skip the checking for the correct number of parameters for that command.

The reason for introducing the ability to have an undefined number of parameters passed in an instruction is to enable more dynamic commands to be created. For instance, the CPU style commands presented in the code_snips download, have some commands defined as three parameters. Optionally those commands could be created so two or three parameters could be passed. If only two parameters are valid, then the target of the operation must be the second parameter. As another example, an INC command could be created that enables the one to six parameters to be passed and have all of them incremented in value in one line of a stimulus script. I am sure users will find a use for this feature.

There is one caution about commands with an undefined number of parameters. The test bench package parsing was created such that user scripting errors were found ASAP. One of the items tested for is a correct number of parameters being passed for every command. By creating an instruction to have an undefined number of parameters, you are telling the parser to skip testing for the correct number of parameters. It then becomes the responsibility of the creator to deal with user input, or ignore errors like too many parameters passed. The code for this change was done in the check_valid_inst procedure.

The predefined stimulus bus record types are intended to be used on BFMs. They are presented as an example of a flexible, standardized interface method. Not that this interface is a standard in industry, but it could be for you applications. This definition of the stimulus bus interface enables the flexibility of ease of change. Say you adopt these record types and create many BFMs using them. If later you find that there is another signal needed in your system, it can be added easily just by changing the record definitions. As a facility to easily set a stimulus bus into a neutral state, a stm_neut function is also provided. This function returns a value that can be directly assigned to the record type, making interfacing simpler. This also provides an example of record assignment and function overloading.

As an example of the stimulus bus record types a packet generator BFM example is provided with the beta release. This BFM implementation demonstrates the following features:

• self generating data, incrementing and random
• data loading from a file and file opening
• data loading from the stimulus file
• dynamic file name in stimulus files
• direct setting of text data from the stimulus file.
• use of the new stimulus port definition.

NOTE: It is required to download the random package from here http://www.synthworks.com/downloads/ package link in order for the example BFM to compile.

The packet generator itself is a generic data generator example. It could be combined with a signaling BFM to implement an complete interface. This is a way of disconnecting the data generation from the actual interface signaling. A data generator can service many different kinds of signaling interfaces. This concept is restated in the BFMs #1 blog post. The request input to the packet generator would originate from a signaling BFM to get new data. In this case the request is implemented in a stimulus command called REQUEST.

The other interesting item presented in the example, something I have never done before, is the assignment of text from the stimulus file. In the example stimulus_file.stm file, the SET_FN command takes the dynamic string and assigns it to the stm_text type input of the BFM. This feature is handy for setting file names dynamically from the test case. The parsing system ensures that strings are nul terminated. This makes it easy to do assignment in a loop. The text string input on the example packet generator BFM is part of the stimulus system, but I did not see it needed for all cases, so left it out of the record definitions.

The Beta version of the test bench package is available here: tb_2011beta2.zip direct download in .zip form. Once I am confident the package has no obvious errors the OpenCores release will be updated.

Included in this release is an updated test bench package header and body files. Some additions and fixes to the ttb_gen utility. Updated documentation, yet to be fully completed. And an example of the new package features and test bench techniques in the form of a packet generator BFM.

If you are a user of the VHDL Test Bench Package and discover a bug or want an enhancement, now is your opportunity provide input. Feel free to post any responses in the comments section of this post.

If you are already using the VHDL Test Bench Package, you can upgrade to the new release, there should be no changes needed to your bhv file.

Enjoy

Sckoarn

VHDL Test Bench Package: Using BFMs #1

Bus Functional Models (BFM's) are the back bone of the VHDL Test Bench system. Using BFM's relieves the scripting system from having to implement detailed signal sequence generation and reaction. Other than your basic READ and WRITE commands, the scripting system should not implement interface signaling. In other words, data path elements outside the DUT should be implemented in a BFM.

For instance, lets say we have a SoC design. It has a processor, a PCIe interface and a high speed optical interface. There is a DDR2 RAM device interface for the processor and temp storage for packet data. This is a very simple design specification and it states we have at least 3 major interfaces to the design. There is no way that the scripting system can act as the DDR2 RAM at the same time as it interacts with the PCIe interface. This is because a script command usually “waits” for signaling to proceed through it's function. i.e. A READ command asserting address, select signals, and waiting for an acknowledge before collecting the read data and terminating the cycle. To solve the problem of concurrency in the scripting system BFM's are used.

A BFM is a functional model of the object of interest. In the case of a DDR2 RAM, the BFM acts and reacts like the real device would. At the same time it should not implement the timing of the RAM interface as those types of models are not BFM's but actual models of the device. Models of devices that include timing can significantly slow your simulations. Avoid using models with timing if possible. BFM's on the other hand may not even model a memory location until it is written to, in other words a sparse memory model. A BFM is purely functional and does not model timing. This is of course unless it is required to model the timing, in which case it becomes a model as apposed to a BFM.

Notice I use the word object when referring to a BFM. A VHDL component can be considered an Object, as it has interface requirements and data access control. In the case of our BFM, it has a specific interface to the DUT and that interface has restrictions on the BFM internal access, i.e through its interface signalling. The test system has a stimulus access port to access various controls and storage, but in a very controlled way. The BFM will have internal signals and variables that are not accessible to the outside itself, they can be considered private to the BFM. Sort of like an object in an OOP language, but not quite.

Creating BFM's is part of the verification effort. If it is well done, the effort can be reused. A well thought out BFM may be reusable in the next project, or for other projects that have similar interfaces. When I create a BFM I look at it as if it was a device. It has an entity and architecture just like any other design object. Besides the obvious DUT interfaces required to exercise the design interface I provide an interface for the test bench. I call it the stimulus access port in the VHDL Test Bench Package documentation, Section 7. Behind the access port is a register set or addressable space. I use the registers (several default ones again and again) to control and configure the BFM.

A refinement I have added to the test bench package is stimulus access port record type definitions. These additions include slave and master versions of the bus definition. The master versions will enable smart objects to use the stimulus bus to control BFMs. Records types for pins enables the pins to be modified and have the over all coding effort, for the change, be reduced. Records for pin types are a very good practice, even in the DUT. The new “standard” record types are part of a new release of the test bench package, (available for Beta testing soon).

To continue on the topic of creating BFM's, if your efforts are part of a large corporation or team, good BFM planning can save a lot of time. If you have many different signalling interfaces and very few data configurations, it may be beneficial to break the BFM's into parts. One part could be the data generation BFM and another part could be the signalling interface BFM. When you create your signalling BFM's you use an interface compatible with the data generation BFM so you can reuse the data generator. So if you had ten different signalling interfaces and only one data type, you saved rewriting or copy/pasting the data generation code nine times over. Not only that but, if your data generation system changes there is only one place to make the change. Modularity is the key word. This kind of structure can save time in the creation of the verification environment as well as in test case writing. Once you have used something, it is easier when you use it again.

When I create a BFM I start by writing a simple specification. Since I use a BFM like a device, accessed through its stimulus port, I create a register map of the control, functionality options and internal memory(s). This enables me to plan out what I will build as well as provides documentation for users. When implementing, you have a specification to code from and this makes the coding easier.

As an example, using my default BMF register set and one memory range:

---

Name              Address     Bit(s) Description

Control Register    0           0    Enable

                                1    Open file trigger, Write a '1'

                                     to this bit to trigger file open

                                     This bit is self clearing.

Configuration       1         3-0    Data coding mode

Register                             0000 Incrementing

                                     0001 Random

                                     0010 Load from file

                                     0011 User Data

Error Register     2                 Read only definition of error indications

Seed Register      3         31-0    Seed value for random number generation

User Data Memory 0x1000 – 0x107F     Bits 7 downto 0 of the data are written

                                       to the addressed location.

The above specification is for the example packet generator BFM provided with the new test bench package version, to be released in the next blog posting.

The stimulus access port provides 32 bit addressing and 32 bit data, which has been enough for everything I have ever implemented. If I have BFM that needs more registers I have all the rest of the 32 bits of addressing to use. The above registers I always put into a BFM because they seem common. As well, it is just a copy/paste away from a working base implementation.

When coding the BFM, I create a test bench for it, using the VHDL test bench package of course. The other thing that one may have to build is a mating BFM for your development. If you are building a SPI Master interface, for instance, you need a slave to react with the master commands, so you might have to build both. This can have the advantage of having to know the interface better and producing both versions of the interface. When the BFM is connected to the DUT for testing, there is a whole test environment to fall back on when there are interface problems.

In the weeks to come, I will post up examples of specific BFM types. The plan is to produce a signaling BFM to partner with the packet generator, a BFM to recover DUT output data, a compare BMF for testing correctness of data and finally a master BFM to demonstrate my vision of the master stimulus bus. The master stimulus bus is new and I will have to do some playing around with it to be able to produce a usage example.  The next post, will be the release of the Beta version of the Test Bench Package.  This includes the BFM and stimulus bus defintion stated above.

Sckoarn

VHDL Test Bench: TTB Gen Plus Beta

Beta Release of TTB Gen Plus 2.0!!!

In preparation for a new release of the test bench package, I have spent a few hours recoding the TTB Gen Plus tcl/tk generation tool. It has one small GUI addition but other than that should look and feel exactly like version 1.0. I am currently working on an update to the VHDL Test Bench Package and want to make it a general update to everything. Part of the package is the generation tool. It helps reduce the overhead of creating a standard test bench implementation. So, as a bonus to you for visiting the blog I would like to offer the Beta version for your testing.

The main enhancement is the removal of physical restrictions on parsing the entity definition. The tool should now parse out any legal VHDL entity definition. The tool will now also generate generics found on the entity in the component and port mapping output to the structure file, entity_name_ttb_str. As a minor addition, an optional build_tb.bat file can be generated for Modelsim and Aldec compilation.

There is one little thing about the generic generation. It is hard for the tool to predict what values should be assigned to generics. So as an initial step they are generated on component and port mapping but commented out for later completion by the user.

If you need to get tcl/tk you can get it here http://www.activestate.com/activetcl/downloads

I personally use the 8.5 version.

There is only one condition on someone that downloads a copy of TTB Gen Plus Beta. That is, if you use it and find a bug, or a feature needed or disliked, you have to post a comment at the bottom of this post. Think of it as a bug report, post up and example of the offending entity declaration.

TTB Gen Plus Beta is downloaded from here: TTB Gen Beta

In the past I have found at least two uses for TTG Gen Plus besides for generating test benches. If you code your entity first, you can use TTB Gen Plus to generate the component definition for you. This can save lots of typing if the entity is large with many pins. Also, the port map definition can be copied into a different structure file, remove the names generated and you have a nice start on the port map coding effort.

I hope that TTB Gen Plus can save you as much typing time as it has me.

Sckoarn

P.S. I will be releasing a Beta version of the VHDL Test Bench Package soon!!

VHDL Test Bench: What is Self Checking??

What is meant by a self checking?

Firstly, a self checking test case is one that gets some status from the DUT and tests that it is correct. The status could be that which is read form a DUT status register. You read the status register and test that it has the correct contents. Or it could be that some BFM implementing a bus protocol, with protocol a checker and internal status register, reading it could indicate that everything is good. When a status is checked there is the possibility that it is wrong. This should cause the simulation to output a message and terminate the run. The message should be as descriptive as possible as you want to find the source of the problem quickly. A test case is self checking in that it tests for some condition and if not correct outputs an indication and terminates the run.

I always implement READ commands in the test bench. Every READ command puts the value read into a common variable. This enables various VERIFY commands to test for conditions after every read. For example, if I had a READ_CPU and a READ_BFM command, and they both put the read value in a variable called v_temp_read, then a VERIFY (word) and a VERIFY_BIT command could look to the same place to get the data to be tested. (some tips about command creation) The VERIFY command is the self checking element of a test case.

When a VERIFY or testing type command checks a value and it is wrong, the output message should have enough detail to enable the problem to be located quickly. I use the assertion facility of VHDL to output useful messages. The file name and line number in that file are part of the instruction and the current value is always available. Specifically the file_name string variable and the file_line integer variable. These variables can be used in the assert statement so the user will know where the error originated. (NOTE: While testing this code it was found that the file_name variable contains nothing. I found this bug in the release version and it will be fixed in a new release, coming very soon.) Below is an example of how I create a VERIFY command. We assume a read took place before a verify is done, and the value is in the v_temp_read variable.

-----------------------------------------------------------------------------

elsif (instruction(1 to len) = "VERIFY") then

v_temp_vec1 := std_logic_vector(conv_unsigned(par1, 32));

assert (v_temp_vec1 = v_temp_read)

report LF & "ERROR: Compare Value was not as expected!!" &

LF & "Got " & (to_hstring(v_temp_read)) & LF &

LF & "Expected " & (to_hstring(v_temp_vec1)) & LF &

"Found on line " & (integer'image(file_line)) & " in file " & file_name

severity failure;

In the above example, if par1 does not match v_temp_read, the assertion will fire. The nice error message will print out stating there was a miss-compare, tell you the received value and the expected value, the file name and line number in the script that caused the error. The “to_hstring” function is available in VHDL 2008. The only other item needed before a user can copy/paste the above, fully functional VERIFY command, is to add the v_read_data std_logic_vector variable to the read_file process. The above command and a few others have been added to the code snips file here: (All code snips are now part of the Opencores distribution)

There is a benefit to having the VERIFY command separate from the READ command in larger verification environments. The scripting system can easily be made to create a READ_VERIFY command, where you both read and verify in the same command. The disadvantage to this that if you have more than one read type command, like DUT reads and BFM reads, you will have to create a READ_VERIFY type command for each read type. And if you wanted to create VERIFY_BIT commands, again one of those for each ready type you want to test. Everything that is read should be tested. If the read and verify are separate commands then one VERIFY command can service all READ type commands.

Another form of self checking relates to the Interrupts and Waiting Post. An unexpected interrupt causes the system to put out a message and terminate the simulation. The self checking part is the process that watches the interrupt output pin, and if not expected causes an assertion. This relates to scripts in that, a script has to inform the interrupt watcher that there will be an expected interrupt, do not terminate the simulation when it comes.

The last form of self checking comes from BFM's. Specifically checker type BFM's. These objects usually monitor some complicated function like a communications protocol, a bus monitor, a ram access checker and so on. The function of these objects is to indicate to the verification system when something goes wrong. For instance, a bus monitor could check the contents of a bus on each rising edge of a clock, and if there are x's on any line indicate an error. Or the monitor could be checking actual timing and or sequences. The topic of monitoring BFM's will be further elaborated on in future posts.

I looked over some home projects and found that I never used a verify type instruction, looking at wave forms seems to have fit my needs. My designs at home are very small and I was just playing around. Projects at work are 1000 times bigger and there are >100 test cases. When I run a regression, when a test case fails, I need to know what and where the failure happened. Good checking and good messages are a must for good verification results.

Sckoarn