VHDL Testbench Package: Register Work Bench

This post is to introduce the Register Workbench. It is intended for those design and verification engineers involved in FPGA/ASIC designs that contain registers and memory. For those readers that are tcl/tk users, it may be noted that the Register Workbench is a tcl/tk application and it is distributed in source form. The package can be downloaded from here: Register Workbench VHDL 0.1

The register set and memory map of a design can be very tedious to produce and maintain. This includes definition, documentation, RTL and verification. It has been seen that some bigger design teams break the task “of registers” down into specific tasks for different people. This introduces delays and inconsistencies for the dissemination of needed information. The documentation gets behind, the RTL gets ahead, and verification does not really know what is correct. I posted test bench package variables and described a centralized table definition. This solves some of the problem but not all of it. The solution is a way to gather, store and generate code and documentation, from a register and memory map definition.

I have crated a tool that enables the definition of memory maps and registers. It is called the Register Workbench. This tck/tk application enables the user to input and modify the definition. The storage format is open and documented in the package with the tool. The storage format is also used internally by the tool, as the file is simply read in and held internally as a list. This is the initial public release of the Register Workbench (RWb). It includes generation geared towards the VHDL Test Bench Package. This includes “defines” for registers names and addresses for inclusion in a stimulus file, generation of VHDL BFM shell containing the defined register block and memory, generation of the VHDL RTL of the register block and some basic HTML documentation generation. It is planed to upgrade and extend the Register Workbench for some time.

What will you gain from using the RWb?

First off, you gain by centralizing the information related to your designs register and memory. This includes document related description text. This means that when changes are made, the change propagates down the design chain almost instantly.

Secondly, you gain stability. Once the generation system is in place, the consistency of the output is guaranteed.

You gain options. The open source, tool code, and storage format enables the you to modify and add to the functionality or definitions.

You gain insight. If you have never used a tool like this on a design that contains registers and memory, you will gain the insight into the benefits.

You gain by being efficient. You will save time by using the tool to assist in your register definition and maintenance. Even if you have to write your own generation code, you will gain. This is the main purpose of the RWb, to save time.

Being the sole coder on this project has opened my eyes to how difficult it is to produce a quality tool. One that will be easy to use and give good information to the user. Most of all how difficult it is to cover all possible operations that a user may take. If you use the RWb and find problems, have comments or suggestions, or would like to contribute, my contact information is included in the documentation. I hope, by using the RWb, that you save time and improve the quality of your efforts ...

Sckoarn

October 10, 2014
Update tool to include "C" #defines header file generation.

Nov. 7, 2014
Update/Upgrade HTML output to include browser and Document Outputs.
This is a big upgrade to the generated HTML output.

VHDL Test Bench Package: License Change & Update

This is a simple notice of changes to the licensing of the VHDL Test Bench Package.  Also a notice that the official release site of the test bench package, Opencores, has been updated.

I recently received an email asking about the licensing of the VHDL Test Bench Package. It is nice to hear from users of the test bench package and readers of this Blog. They decided to not use the test bench package because of the licensing.

The test bench package was under the GNU General Public License, as published by the Free Software Foundation. I will not go over the details, as it is easy to obtain and can be read. The license covered the four files, ttb_gen_gui (and others), template_tb_bhv.vhd, tb_pkg_head.vhd and tb_pkg_body.vhd. The output from ttb_gen, or the use of the template could imply a derived work. This would cause the test bench you created to have to be punished / delivered with the same license as the package. This can cause problems for some businesses.

The license for the VHDL Test Bench Package has been changed to the BSD-2 clause license. This change is reflected on the Opencores site at: Test Bench Package.   If you are using previous versions of the test bench package for business purposes, you should update to the latest version.   The license change ensures that the package conveys my intent, freedom of use.

Just before the license update to he test bench package, I copied all content from my privet site to Opencores.  This includes the example and code snips that were available there.   I now believe that the Opencores site is the most current offering of the test bench package.  I will eventually remove the links, to offerings of the older test bench package, from this blog.

All the Best,

Sckoarn