VHDL Test Bench Package: Functional Coverage

Functional Coverage?? You may think this topic only applies to current methodologies like those based on sophisticated OOP languages using randomization and coverage matrices. This is not true, the scripts created to test the DUT are the functional coverage in a script based system.

When you are verifying a product, you will want the quality to be as high as possible. This all stems from good planning. There should be a written product specification so that everyone knows what they are building. From this specification more specifications can be created that spec out the low level details, i.e. your FPGA or ASIC. Part of the verification effort is to create a test plan. This will include extracting the functional requirements from various sources. The first source of functionality comes from the requirements specification. The other source of most of the detailed functionality comes from the design specification. This is unless the requirements specification has ALL the details needed to prove the functionality of the device. I have found this to be very rare that one document is the source of all functionality definition. The quality of the specification is usually reflected in the quality of the design and testing. A poorly defined device is hard to design let alone verify.

The functionality extracted from the specifications should be collected and documented. I usually make a table in the test plan that contains all the functionality. The table can often be more than ten pages of functional points, one point per row. By doing the plan, you review all the functionality and prepare yourself for the task.  List for each functional point a test case to cover it. This could be placed in a column in the same row as the functional point.  If the functionality is covered by many test cases, they should all be listed. By doing this exercise of planning you will have produced a matrix of functional coverage and the test cases that do the covering. Be sure to make the test cases self checking so you know that the testing is being done and verified.

How do you know you got all the functionality?

One facility that is common is, code coverage. Code coverage tells you which lines of code / which branches were taken, when you ran a simulation. Code coverage does not tell you if any of the functionality simulated was correct. If you run all of your test cases and combine the code coverage you will get an insight into how well the design was exercised. Missed lines of code and branches will some times uncover missed or unknown functionality. Missed lines may be missed because they were unreachable. By analyzing each missed code line, the verification person can speculate and determine why each item was missed.

The VHDL Test Bench Package can be used to create a verification system that will enable full functional requirements of a FPGA or ASIC design to be verified. This is achieved by using test cases to prove functional points.

Sckoarn