Hello everyone.
I have been busy with work and life
over the past two years. This makes it difficult to find the time or
the will to publish new articles. After a full day of coding and
verification, I just do not have the drive to write and code in my
spare time.
I am currently working with a
consulting group called XtremeEDA. We are specialists in the field
of verification and design of integrated circuits. Clients of
XtremeEDA are those companies that produce silicon designs of all
sizes and applications. Some of the clients of XtremeEDA are the
biggest players in the semi-conductor industry. This includes EDA
vendors.
The contracts I have worked on, this
past couple of years, have been a VHDL DO-254 project and some
smaller projects proving IP for large SOC designs. I plan to post
more information about how the VHDL Testbench can be used for DO-254
verification efforts.
This post is mainly a call for readers
to post up some information about how they used the VHDL Testbench
for their verification efforts. With the number of pages having been
read, above 10,000 there has to be a few that actually used the VHDL
Testbench package for something. For those that did use the VHDL
Testbench, I like to hear how it was used, problems encountered,
solutions to the problems and any general description of usage. I am
sure that future readers will find the stories interesting and
possibly useful. Hearing from users may also inspire me to write
more about VHDL Testbench usage.
NOTE: If you do post something, please
do not post proprietary information. If you work for a company then
you most likely know what this means. For those that do not, please
do not post details about your “design” if you do not own it.
For test bench users, you can describe everything except details
about code produced in BFMs and instructions, unless you are the
owner.
To post something, simplely add a comment to this post. Once I reveiw it, as long as it is realated to this blog, it will be published.
Sckoarn
Sckoarn
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