This is a simple notice of changes to
the licensing of the VHDL Test Bench Package. Also a notice that the
official release site of the test bench package, Opencores, has been
updated.
I recently received an email asking about the licensing of the VHDL Test Bench Package. It is nice to hear from users of the test bench package and readers of this Blog. They decided to not use the test bench package because of the licensing.
The test bench package was under the GNU General Public License, as published by the Free Software Foundation. I will not go over the details, as it is easy to obtain and can be read. The license covered the four files, ttb_gen_gui (and others), template_tb_bhv.vhd, tb_pkg_head.vhd and tb_pkg_body.vhd. The output from ttb_gen, or the use of the template could imply a derived work. This would cause the test bench you created to have to be punished / delivered with the same license as the package. This can cause problems for some businesses.
The license for the VHDL Test Bench Package has been changed to the BSD-2 clause license. This change is reflected on the Opencores site at: Test Bench Package. If you are using previous versions of the test bench package for business purposes, you should update to the latest version. The license change ensures that the package conveys my intent, freedom of use.
Just before the license update to he test bench package, I copied all content from my privet site to Opencores. This includes the example and code snips that were available there. I now believe that the Opencores site is the most current offering of the test bench package. I will eventually remove the links, to offerings of the older test bench package, from this blog.
All the Best,
Sckoarn
Sckoarn,
ReplyDeleteI'm working on a personal FPGA project (I did ASICs many many moons ago) and need to improve my productivity. Since I don't have time for a high learning curve, I'm looking for tools that deliver high return on a modest time investment. I wanted to give you an FYI that I'll be having a look at your package ... when I get to my next milestone and can catch my breath so to speak.
Cheers,
John
Hey John,
ReplyDeleteIt is so rare to get comments here that I would expect that you will have no problems. I equate low comments to ease of use or that users are getting what they need.
But feel free to ask for help if needed.
Sckoarn
Sckoarn,
ReplyDeleteI have just started a new position and have been introduced to your VHDL Test Bench package and the ttb_gen_gui tool. By the time I joined, the engineer I am working with had already used your tool to create what is now a fully working testbench. Whilst this VHDL testbench is working great, for various reasons I have been asked to look into developing a SystemVerilog based framework. I would really like to use your testbench generator, so do you have any plans to create a version which outputs SystemVerilog instead of VHDL?
thanks,
Kevin
Sckoarn,
ReplyDeleteI clicked on the 'SystemVerilog Directed Testbench' link on the r/h side of this web page, logged into my opencores account and can see your SystemVerilog directed testbench appears to be the equivalent of your VHDL one. Many thanks!
Kevin