Introduction

Hello all you VHDL coders out there.

I have initially posted this on the edaboard.com blogs, but their blogger is not as flexible as this system. So this will be the new and continuing place for my postings. Sckoarn

Welcome to the GNU VHDL Test Bench Package Blog!!

I have been coding VHDL for 15 years now. The coding I did was 95% for verification. From my beginnings as a Verification person using VHDL, I have used a test bench system. A simple scripting system that has proven itself to enable quality designs to be produced. The system I have used and have published, has been significantly upgraded in the past 15 years of use.

The link to the GNU VHDL Test Bench Package is here:

http://opencores.org/project,vhld_tb

Be sure to download the whole thing including documentation and example.

I published this package because the company I was with was looking to change to a more modern verification methodology. Since I had found it so useful, I wanted to share it with anyone that could use it. The package has been downloaded, on average, about 2-3 times per day over the past 4 years. This indicates to me that many are already using the package. This also indicates to me that simple scripting, as a methodology, is not completely dead and that VHDL is still used by many.

So, what is the GNU VHDL Test Bench Package?

The test bench package is a frame work that enables the objects of a test system to be controlled. The test bench package is also, a collection of procedures that enable the user to create their own scripting language. The frame work is the structure that can be automatically generated around a VHDL entity. (automatically provided the coding is done in a specific way.) The frame work gives the user a “place” to put all the interface BFM type code. The scripting system enables the user to create textual scripting commands to control the simulation and it's objects. A test writer, can use the scripting commands to write test cases without having to know any HDL. The script is a simple text file that can be created by any text editor. Scripts can also be generated, which is an advanced topic. The package enables the user (designer/verification person) to create a test bench and be bringing the design out of reset within hours. Scripts can be changed, using existing commands, and NO recompile is needed.

The test bench package has been tested on all major simulators as well as GHDL, the free VHDL simulator.

Why should/would anyone use the GNU VHDL Test Bench Package?

1. Your tool set or coding knowledge limits you to the use of VHDL.
2. You have no established way of doing verification, you use an ad-hawk method for each design.
3. Your designs are not huge SOC devices. Though you can use the test bench package to assist in the verification effort of SOC devices, but it is not a task for a novice user.
4. You want to design, not design verification systems. The package enables a VHDL coder to concentrate more on the design and verification effort and less on the verification system/environment.
5. You are a lone Verification person in a bigger group. With some of the above constraints, you want to organize the verification effort so the whole group can work under a single method.
6. The test bench package is industry proven.
7. The test bench package is free.

I have performed the verification function under all of the above constraints. Some of the designs I have verified have been SOC devices and even multi-device designs.

Why write this blog?

As stated above, the test bench package has been used, by myself and many others, for 15 years. Over that time frame I have changed the way I use the package, leaning from past efforts. I would like to help new users of the VHDL test bench package to by-pass some of the pitfalls I have encountered. The test bench package is very versatile and it can help make life easier, or not so.

My only goal, in writing this blog, is to help new users become experienced users ASAP. This will help you produce better quality designs with less time and effort.

By writing this blog, I am not stating that using the VHDL test bench package is the best way to do verification. The VHDL test bench is a 1990's methodology, and today many believe in the OOP languages that have evolved to try and meet the task of verification. It is not the purpose of this blog to compare or comment on the differences of OOP methods and the VHDL test bench package.

What do I plan to write about in this blog?

I will be adding to this blog over the coming weeks, there are lots of little things that can be said about usage. Topics like BFM's, modelling, scripting, complex designs, reuse, usage tips and external script generation.

If you are interested in having me write about a specific topic, regarding the VHDL test bench package, feel free to post up your request or send me a privet message.

Cheers,

Sckoarn