VHDL Test Bench Package and VHDL 2008

In an effort to remove the need for the std_logic_1164_additions.vhdl package, I started looking at compiling with the 2008 switch turned on. ( I use the Modelsim simulator PE Student addition 10.1) One of the reasons I want to get rid of the additions package is because it is about 2000 lines long. The student addition of the simulator is performance limited by the number of lines of code in your design and test bench. The number 10,000 lines comes to mind. So the additions package uses 10% of that, IMO that is a high percentage, for something that is unused by the basic test bench structure.

So, why was it included in the first place? At the time, the additions package provided the to_hstring function that is very handy to convert your std_logic_vector to a text string, in hex. This need arose when an evaluation of different tool performances was done. This made it so I had to change the tb_bhv file so it did not use tool specific VHDL functions. (namely the Modelsim std_developerskit) I used std_developerskit functions to format messages to the user when reporting compared values. The needed, tool independent, functionality was found in the additions package. The functions in the additions package can be copied/modified and placed in the VHDL test bench package if needed. The removal of the std_logic_1164_additions from the compile stream will save space for more design and other useful test bench code when using PE Student addition.

What I did was to put the -2008 switch in my compile line that pertains to the test bench package like so: “vcom -2008 vhdl/tb_pkg_header.vhd vhdl/tb_pkg_body.vhd” and commented out all lines that pertained to std_logic_1164_additions.vhdl package use. It compiled and ran with no errors. NOTE: I had not used to_hstring in any file. When I compiled without the -2008 switch the results were the same, a working simulation.

I have never evaluated the test bench package for compilation under the latest VHDL standard. It appears like the package itself is standalone without the need for the std_logic_1164_additions package. So when you use the test bench package you can comment out the library and use statements that pertain to the std_logic_1164_additions package.

When using Modelsim you can make use of their std_developerskit for many useful facilities. Thought in inclusion of std_developerskit will use ALL of the design space in the Modelsim PE Student application. Those of you that have real tools, you can use what is needed to get the job done and not worry so much about performance.

Sckoarn