The VHDL Test Bench Package vs. the Test Harness

 VHDL Test Bench Package vs. The test harness

I have seen posted lately and have seen people use what they call a test bench. Some call it a harness, this name could be coming from the Verilog world. To put it in VHDL terms, the test bench is an architecture that instantiates the Design Under Test (DUT) and has several processes that interface to the DUT. One of those processes is the clock process, this is very standard. Every system has to have some kind of clock generation process. The other process is called something like stimulate or simulate. It “is” the test, and wiggles inputs and waits for time, wiggles more inputs. Many of these kinds of test harnesses do not even prove that something is correct. I think the user just looks at wave forms and decides it is correct or not. This system would be useful for testing something simple like an AND gate. But if your DUT is complicated the test harness suffers from several problems.

1. You have to recompile your test bench every time you make a change to the test.
2. Unless you have more than one test harness, you only have one test.
3. If your design changes, and you have more than one test harness, each harness has to be modified to test the changes.
4. Since there is only one test per harness, it is difficult to implement multiple test scenarios.
5. Reuse of test bench code is not likely from design to design.

With the VHDL Test Bench Package all of the above issues are removed from concern.

1. You can run test after test and not have to recompile anything.
2. You can have many many tests all running from the same, single test bench.
3. If there are design changes that affect signalling in some way, it only has to be modified in one place to cause all tests to be updated. ie. Design changes
4. You can have many test case writers creating test cases at the same time on the same test bench.
5. You will find that many commands you create will be reusable in every test effort.

The VHDL Test Bench Package is a programmable script parser that exists in an architecture. By default (and generation) the VHDL test bench is a multi file set with the test bench architecture and DUT architecture connected in a VHDL top level test bench structure. The included generation program, generates entity and architecture files to connect the test bench to the DUT. The generation program also copies and edits the test bench architecture from a template. A user can also use the template architecture within any entity, making it an internal DUT BFM. Though it is a multi file system, a simple build script makes it easy to compile as needed.

Though the VHDL Test Bench Package system is more complicated than a simple harness test bench, I believe the small amount of extra effort required to create is offset by the capabilities it enables. But when the design is changing while you are trying to test it, you may find the effort to update hard coded test benches overbearing.

I will make posts in the near future that will help get users up to “high speed” in no time. Please post any comments regarding this post or what you would like to see posted next.

Sckoarn