VHDL Test Bench: Usage Tips I Interrupts and Waiting

VHDL Test Bench: Usage Tips I

If the test bench contains commands that wait for an event, it is good to have a watch dog to terminate the simulation if the event never happens. The main reason for this is so that your over night regression does not get stuck on test #2, and waste the whole night.

A Script command might look something like this:

WAIT_IRQ -- wait for the IRQ

The test bench code could look like this:

For some cases maximum wait time may need to be modifiable. In this case make the constant, in the above example, a signal and create a command that enables you to change it's value.

 

 

If the DUT has an interrupt type output(s), the output(s) should be monitored by a process. This will enable the test to “expect” the signal or to catch it, if it asserts unexpectedly. First, a switch is needed to disable the monitor for the expected IRQs. So a boolean signal can be used as a switch. Then a command that will enable the state of the switch to be changed. Finally, a process to monitor the IRQ, clock by clock, and assert the appropriate message when the IRQ asserts.